Web edition: May 22, 2012
To err is not only human — it’s silicon. Computer chips that are designed to make mistakes are faster, smaller and more energy efficient than their perfect counterparts. Scientists interviewed dozens of humans about acceptable levels of error in video visuals and then used a mathematical algorithm to fine-tune a chip to take shortcuts and make tolerable processing mistakes. Regular processing yields a sharp image (left), but a relative error of 0.54 percent is still pretty good (center), the team reported May 15 at the ACM Computing Frontiers conference in Cagliari, Italy. The chip with a 7.58 percent error rate (right) is about 15 times more efficient than an ordinary chip in speed, space and energy use. Led by Krishna Palem of Rice University in Houston, the researchers have built 10 chip prototypes and the hardware will go into thousands of low-cost I-slate tablets for use in classrooms in India. The researchers are now investigating tolerable error rates for chips in hearing aids.
A. Lingamneni et al. Algorithmic methodologies for ultra-efficient inexact architectures for sustaining technology scaling. ACM Computing Frontiers conference, Cagliari, Italy, May 15, 2012. Paper: [Go to]